Customized parameterization of read parameters after a decoding failure for solid state storage devices

ABSTRACT

Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a codeword of the memory: obtaining at least three read values of the codeword; calculating a signal counts metric value from the at least three reads; computing an optimal reference voltage offset from the signal counts metric and a correlation between optimal reference voltage offsets and a signal counts metric associated with the memory; determining a new center read reference voltage based on a current center reference voltage and the optimal reference voltage offset and performing at least one subsequent read of the codeword following the decoding failure utilizing the new center read reference voltage.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 17/115,940, filed Dec. 9, 2020, now U.S. Pat. No. 11,301,323 issued Apr. 12, 2022, which is a continuation of U.S. application Ser. No. 16/259,346, filed Jan. 28, 2019, now U.S. Pat. No. 10,891,189, issued Jan. 12, 2021, which are hereby specifically incorporated by reference herein in their entirety.

SUMMARY

In one embodiment, a method comprises performing the following steps, in response to a decoding failure of one or more of a page of a memory and a codeword of the memory: obtaining at least three read values of the one or more of the page and the codeword; and processing the at least three read values to determine one or more read parameters comprising one or more of: (i) at least one log likelihood ratio, and (ii) at least one center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of a plurality of regions of the memory and wherein the one or more determined read parameters are used for one more of a decoding of the page and the codeword following the decoding failure and a subsequent read operation following a successful decoding of the one or more of the page and the codeword.

In some embodiments, the signal counts indicate a location of a current center reference voltage with respect to a substantially optimum center reference voltage. In one or more embodiments, the step of processing the at least three read values, or a portion thereof, is performed using a hardware acceleration block, firmware, a state machine and/or hardware.

Other illustrative embodiments include, without limitation, apparatus, systems, controllers, methods and computer program products comprising processor-readable storage media.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of an illustrative solid state storage system, in accordance with one or more embodiments of the present disclosure;

FIG. 2 illustrates a flash channel read path with read reference voltage tracking, in accordance with some embodiments of the present disclosure;

FIG. 3 is a graph of cell voltage distributions for a normal hard decision read operation in a solid state memory device, in accordance with some embodiments of the present disclosure;

FIG. 4 illustrates an example of three read operations for an exemplary flash memory device, according to some embodiments;

FIG. 5 illustrates an example of a log likelihood ratio (LLR) lookup table (LUT), according to an embodiment of the disclosure;

FIG. 6 illustrates an example of a multiple LLR LUT, according to one embodiment of the disclosure;

FIG. 7 illustrates LLR Values as a function of a Signal Counts Metric, for an exemplary flash memory device;

FIG. 8 illustrates a linear fitting to fit the LLR/signal metric pairs of FIG. 7 , for the exemplary flash memory device;

FIG. 9 is a flow chart illustrating an exemplary implementation of an error recovery process for read parameter prediction, according to one embodiment of the disclosure;

FIG. 10 is a flow chart illustrating an exemplary implementation of an error recovery process using customized LLR values, according to an embodiment;

FIG. 11 illustrates an exemplary LLR calculator that uses the disclosed read parameter estimation techniques for a linear model to calculate LLR values, according to at least one embodiment of the disclosure;

FIG. 12 illustrates various regions for an exemplary LSB page of the exemplary flash memory device;

FIG. 13 illustrates various regions for a representative CSB page of the exemplary flash memory device;

FIGS. 14 and 15 illustrate exemplary implementations for differentiating regions for reference voltages R₂ and R₆ for the representative CSB page of FIG. 13 , according to various embodiments;

FIG. 16 illustrates the center voltage reference (V_(ref)) read parameter as a function of the Signal Counts Metric, for the exemplary flash memory device;

FIG. 17 is a flow chart illustrating an exemplary implementation of an error recovery process using customized center V_(ref) values, according to one embodiment of the disclosure;

FIGS. 18A and 18B, collectively, comprise a flow chart illustrating an exemplary implementation of an error recovery process using customized LLR values and center V_(ref) values, according to an embodiment;

FIG. 19 illustrates an exemplary parallel implementation of an error recovery process using customized LLR values and center V_(ref) values, according to one embodiment of the disclosure;

FIG. 20 illustrates an exemplary firmware implementation of an error recovery system using customized LLR values and center V_(ref) values, according to some embodiments;

FIG. 21 illustrates an exemplary hardware implementation of an error recovery system using customized LLR values and center V_(ref) values, according to one or more embodiments;

FIG. 22 illustrates exemplary hardware tables for supporting LLR calculations, according to an embodiment of the disclosure;

FIG. 23 is a flow chart illustrating an exemplary implementation of a state machine discussed in conjunction with FIG. 22 , according to one or more embodiments of the disclosure; and

FIG. 24 illustrates a processing platform that may be used to implement at least a portion of one or more embodiments of the disclosure.

DETAILED DESCRIPTION

Illustrative embodiments will be described herein with reference to exemplary solid state storage devices and associated storage media, controllers, and other processing devices. It is to be appreciated, however, that these and other embodiments are not restricted to the particular illustrative system and device configurations shown. Accordingly, the term “solid state storage device” as used herein is intended to be broadly construed, so as to encompass, for example, any storage device implementing the read parameter prediction techniques described herein. Numerous other types of storage systems are also encompassed by the term “solid state storage device” as that term is broadly used herein.

In one or more embodiments, read parameter estimation techniques are provided that obtain additional information from existing multiple read operations to customize one or more read parameters for data recovery. In some embodiments, exemplary error recovery techniques are provided that process three or more read values of a given codeword or page to determine read parameters comprising (i) LLRs, and/or (ii) center V_(ref), as discussed further below.

FIG. 1 is a schematic block diagram of an illustrative solid state storage system 100. As shown in FIG. 1 , the illustrative solid state memory system 100 comprises a solid state storage control system 110 and a solid state storage media 150. The exemplary solid state storage control system 110 comprises a controller 120 and an encoder/decoder block 130. In an alternative embodiment, the encoder/decoder block 130 may be implemented inside the controller 120.

As shown in FIG. 1 , the controller 120 comprises a page-level read reference voltage parameterization process 600, discussed below in conjunction with FIGS. 6A and 6B, to implement the read parameter prediction techniques described herein. The encoder/decoder block 130 may be implemented, for example, using well-known commercially available techniques and/or products. The encoder within the encoder/decoder block 130 may implement, for example, error correction encoding, such as a low-density parity-check (LDPC) encoding. The decoder within the encoder/decoder block 130 may be embodied, for example, as a hard decision decoder, such as a hard decision low-density parity-check (HLDPC) decoder.

The solid state storage media 150 comprises a memory array, such as a single-level or multi-level cell flash memory, a NAND flash memory, a phase-change memory (PCM), a magneto-resistive random access memory (MRAM), a nano RAM (NRAM), a NOR (Not OR) flash memory, a dynamic RAM (DRAM) or another non-volatile memory (NVM). While the disclosure is illustrated primarily in the context of a solid state storage device (SSD), the disclosed read parameter prediction techniques can be applied in solid state hybrid drives (SSHD) and other storage devices, as would be apparent to a person of ordinary skill in the art based on the present disclosure.

FIG. 2 illustrates a flash channel read path 200 with channel tracking-based read retry voltage adjustment in accordance with some embodiments of the present disclosure. The read path 200 includes a flash device 202 having an array of memory cells, or another type of non-volatile memory. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage technologies that can benefit from the read parameter prediction techniques disclosed herein.

Read reference voltages 226 are applied to the flash device 202 by a read control device 224 in a series of N reads. Each memory cell is read N times, and the N reads result in read data 204 containing N bits per memory cell as a quantized version of the stored voltage on the memory cell. The read data 204 is buffered in a read buffer 206, and buffered read data 210 from read buffer 206 is provided to a log likelihood ratio (LLR) generation circuit 212 (or likelihood generator, which can also be adapted to use plain likelihood values). The N bits for a memory cell are mapped to log likelihood ratios 214 for the memory cell in log likelihood ratio generation circuit 212. In some embodiments, the log likelihood ratio generation circuit 212 contains a lookup table that maps the read patterns in buffered read data 210 to log likelihood ratios 214.

A tracking module 230 receives the buffered read data 210 from the read buffer 206, or from any other suitable source. Generally, channel tracking techniques adapt to the changes in read reference voltages to maintain a desired performance level. Adaptive tracking algorithms typically track variations in the solid state storage channel and consequently, help to maintain a set of updated channel parameters. The updated channel parameters are used, for example, to adjust read reference voltages. United States Published Patent Application No. 2013/0343131, filed Jun. 26, 2012, entitled “Fast Tracking for Flash Channels,” and/or United States Published Patent Application No. 2015/0287453, entitled “Optimization of Read Thresholds for Non-Volatile Memory,” (now U.S. Pat. No. 9,595,320) incorporated by reference herein in their entirety, disclose techniques for adapting read reference voltages.

The tracking module 230 identifies the intersection point between neighboring voltage distributions for a memory cell, in a known manner, and provides read reference voltage level V_(REP0) 232, including the read reference voltage V_(REF0) corresponding to the intersection. When the read reference voltage V_(REF0) corresponding to the intersection is used for the soft read operation, it will result in a reduction in the bit error rate. The read reference voltage V_(REF0) is used in some embodiments as the first read reference voltage of a read retry operation, and additional read reference voltages around V_(REF0) to obtain substantially all possible log likelihood ratio values. The tracking module 230 thus generates the read reference voltage level V_(REF0) 232 to be used in read retry operations. In other embodiments, V_(REF0) may not correspond to the intersection of the distributions depending on the tracking algorithm design, tracking inaccuracy, or the actual channel distributions deviating from Gaussian behavior in either the peak or the tail. In other situations, V_(REF0) may coincide with the intersection of the distributions but may not be applied first and that would be accounted for in the calculations in 212 and 224.

The tracking module 230 also tracks the voltage distributions 234. In some embodiments, the tracking module 230 calculates the voltage distribution means and variances for each voltage distribution 234 corresponding to each possible state in each memory cell. The voltage distributions 234 can be calculated in any suitable manner based on the read data. As an example, the tracking module 230 can operate as disclosed in U.S. Published Patent Application No. 2013/0343131, filed Jun. 26, 2012, entitled “Fast Tracking for Flash Channels,” incorporated by reference herein in its entirety. In some embodiments, the tracking module 230 tracks intersections without estimating means or variances.

For a two-state memory cell, or single-level memory cell, the tracking module 230 estimates the means and variances of the voltage distributions of states “1” and “0”, as well as the read reference voltage V_(REF0) that most reduces the bit error rate and which likely lies at the intersection of those distributions, in a known manner.

The tracking module 230 provides the voltage distributions 234 to the log likelihood ratio generation circuit 212 for use in updating the log likelihood ratio lookup table. The log likelihood ratio generation circuit 212 is used to calculate likelihood values 214 for decoding by an LDPC (low-density parity-check) decoder 216 that generates decoded data 220. The log likelihood ratio generation circuit 212 also determines where to place the other N−1 read reference voltages around V_(REF0) 232 based on the voltage distributions 234 and on the read reference voltage V_(REF0) 232 to obtain substantially all possible log likelihood ratio values when the read patterns in buffered read data 210 are mapped to log likelihood ratios. The log likelihood ratio generation circuit 212 determines where to place the other N−1 read reference voltages around V_(REF0) 232, updates the lookup table, and provides the N−1 read reference voltage levels 222 to a read controller 224. It is important to note that the division of functionality is not limited to the example embodiments disclosed herein. For example, in other embodiments, the tracking module 230 calculates and provides read reference voltages around V_(REF0) 232 and provides those voltages to the log likelihood ratio generation circuit 212, rather than the log likelihood ratio generation circuit 212 determining where to place the other N−1 read reference voltages around V_(REF0) 232, and these divisions of functionality are to be seen as equivalent.

The read reference voltages are stored in log likelihood ratio generation circuit 212 in some embodiments, as calculated based on the log likelihood ratio lookup table in log likelihood ratio generation circuit 212 and on the voltage distribution means and variances 234 from tracking module 230.

The read controller 224 controls read retry operations in the flash device 202, providing each of the N read reference voltages (including V_(REF0) 232) to be used when reading the memory cells in the flash device 202. The read controller 224 initiates N reads of a page, with the first read using read reference voltage V_(REF0) in some embodiments, and with the subsequent N−1 reads at read reference voltages around V_(REF0) as determined by log likelihood ratio generation circuit 212.

FIG. 3 is a graph 300 of cell voltage distributions 311 through 318 for a normal hard decision read operation in a TLC flash memory device, in accordance with some embodiments of the present disclosure. The exemplary TLC flash memory device is a BiCS3 NAND flash memory from Toshiba Memory America, Inc. The resulting voltages read from the memory cell thus appear something like the distributions 311-318 shown in the graph 300 of FIG. 3 , rather than eight distinct discrete voltage levels corresponding to the eight states 111, 110, 100, 000, 010, 011, 001, 101 at the corresponding target state voltage levels. Each distribution 311-318 will have a mean roughly equal to the target voltage for the respective state, and the variance will depend upon the noise. Because the voltages on the memory cell are not accurate, the voltages read back can vary according to the distributions 311-318. In some embodiments, during the initial read of the memory cell, reference voltages R₁ (i=1, 2, . . . , 7) (e.g., R₁ through R₇) are used during a read to determine the state of the memory cell, returning hard decisions about the state of the memory cell.

For example, in general, if the read voltage is below reference voltage R₁, a decision indicates that the memory cell is determined to be in state 111. If the read voltage is above reference voltage R₁ and below reference voltage R₂, a decision indicates that the memory cell is determined to be in state 110, and so on.

The first, second, and third bits in a given state are often referred to as the most-significant bits, center-significant bits, and least-significant bits (MSB, CSB, LSB), respectively. In some embodiments, the read operation is divided into a process of reading least significant bit (LSB) pages, center significant bit (CSB) pages and most significant bit (MSB) pages. States 111, 011, 001 and 101, for example, correspond to a least significant bit value of 1, and states 110, 100, 000 and 101 correspond to a least significant bit value of 0. When reading the least significant bit, for example, the reference voltages R₁ and R₅ are applied to the memory cell to obtain the least significant bit.

While FIG. 3 illustrates the cell voltage distributions for a TLC flash memory, the disclosed read parameter prediction techniques can be applied to SLC, MLC, QLC, etc. and other flash memory systems, as would be apparent to a person of ordinary skill in the art.

For each R_(i) shown in FIG. 3 , a pair (V_(oi), P_(i)) can be derived for each page number, where V_(oi) is the substantially optimal reference voltage that substantially minimizes the bit error rate, and P_(i) is the corresponding page number.

Read Parameter Prediction Techniques

In one or more embodiments, techniques are provided for read parameter prediction using three or more read operations of a solid state storage device, such as a flash memory. In flash memory systems, a single-read produces hard information (such as bit estimation of “0” or “1”). If hard information is not sufficient to recover the data, additional read operations are usually issued to generate soft information for a decoding process. The way the soft information is generated from multiple read operations has a direct impact on the error recovery performance. The present disclosure discloses efficient methods where read parameters, such as an LLR and center voltage reference (V_(ref)) are predicted from three initial read operations. The predicted LLR provides more accurate soft information for an error correction decoder (such as an LDPC decoder); while the estimated center V_(ref) is expected to reduce the raw bit error count. In either case, the error recovery performance is improved.

Multiple Read Operations in Flash Memory

For an initial error recovery process in a flash memory, a single-read operation is typically issued, and the hard information is mapped into log LLR values that are passed to error correction decoder to recover the data. If the decoder fails to decode, then additional read operations are issued (in some cases, more single-read operations with different reference voltage values are issued before multiple read operations.). FIG. 4 illustrates an example 400 of three read operations for an SLC device, according to some embodiments, where a center read operation (denoted by T_(c)) and two shoulder read operations (denoted by T_(i) and T_(r)) are issued. The three read operations yield four regions, denoted in FIG. 4 by regions A, B, C and D. Region A is interpreted as a binary 1 and region D is interpreted as a binary 0. Each region A, B, C and D corresponds to a reading pattern from the three read operations and therefore each region is differentiable. For example, region A is labelled by ‘111’, region B is labelled by ‘011’, region C is labelled by ‘001’ and region D is labelled by ‘000’.

Bits falling in each region are usually mapped to an LLR value using a predetermined lookup table. FIG. 5 illustrates an example of an LLR lookup table (LUT) 500, according to an embodiment of the disclosure. The assigned LLR values in FIG. 5 are then sent to a decoder for soft decoding. If the decoding still fails, other error recovery steps/plans are executed. The information derived from multiple read operations results in labelling each region using FIG. 4 , guides the subsequent LLR mapping.

According to one or more embodiments of the present disclosure, additional information is obtained from the existing multiple read operations, to customize one or more read parameters for data recovery, as discussed hereinafter. In some embodiments, exemplary error recovery techniques are provided that process three or more read values of a given codeword or page to determine read parameters comprising (i) LLRs, and/or (ii) center V_(ref), as discussed further below.

Available Data Statistics

A signal count of a specified region is defined as the number of bits falling in that region. In the example of FIG. 4 , the signal count, S, of each region (A, B, C and D) can be represented by S_(A), S_(B), S_(C) and S_(D), respectively. If reference data is available, the signal counts of the four regions are also available for the given read operations. The values of signal counts provide insights on the center V_(ref) location with respect to a substantially optimum value, as well as the reliability of the bits falling in those regions. For example, if S_(B)≈S_(c), the center V_(ref) T_(c) is likely to be close to a substantially optimum value, and the bits falling in regions B and C have a similar reliability level; if S_(B)<<S_(C), the center V_(ref) T_(c) is likely to locate to the right of the substantially optimum value and the bits falling in region C might have a higher reliability level than those bits falling in region B. The following sections explain how LLR values and center V_(ref) are estimated using these bin counts, in some embodiments of the disclosure.

LLR Estimation

In a flash memory, neighboring bits are mapped to the same LLR value. For example, the LLR of region A is mathematically defined in equation (1),

$\begin{matrix} {{{LLR}(A)} = {\log\frac{{number}\mspace{14mu}{of}\mspace{14mu}{bits}\mspace{14mu}{read}\mspace{14mu}{in}\mspace{14mu} A\mspace{14mu}{that}\mspace{14mu}{were}\mspace{14mu}{programmed}\mspace{14mu}{as}\mspace{14mu}{``0"}}{{number}\mspace{14mu}{of}\mspace{14mu}{bits}\mspace{14mu}{read}\mspace{14mu}{in}\mspace{14mu} A\mspace{14mu}{that}\mspace{14mu}{were}\mspace{14mu}{programmed}\mspace{14mu}{as}\mspace{14mu}{``1"}}}} & (1) \end{matrix}$ Likewise, LLR(B), LLR(C) and LLR(D) can be defined in a same manner.

Conventionally, one or more predetermined LLR-LUTs are used for LLR mapping. FIG. 6 illustrates an example of a multiple LLR LUT 600, according to one embodiment of the disclosure. Once three read operations are issued, the decoder tries to decode the data with LLR LUT 1, 2, . . . , N of FIG. 6 , e.g., sequentially, until one of the LUTs successfully recovers the data.

Usually region A and D in FIG. 4 are regarded as high reliable regions, where bits are considered to be 0 and 1, respectively, with a high probability. Therefore, regions A and D are usually assigned LLR values with large absolute values (for example, −7 and 7 as shown in FIG. 6 ). The sensitive regions are B and C, where errors typically occur. The values of LLR(B) and LLR(C) in FIG. 6 are therefore important for error correction decoder. A predetermined LUT, such as the LUT of FIG. 6 , lacks the flexibility to accommodate various noise patterns in the data. The following discussion shows how to estimate LLR(B) and LLR(C) dynamically using signal counts of different regions. LLR(A) and LLR(D) can be estimated in a similar manner, as would be apparent to a person of ordinary skill in the art, based on the discussion herein.

The correlation between LLR values and signal counts metric is first derived. For each codeword, the values of LLR(B) and LLR(C) can be calculated using equation (1), given the availability of genie data. With 3 read operations, the signal counts S_(B) and S_(C) are also available. It can be shown that both LLR(B) and LLR(C) have a positive correlation with the signal counts metric (S_(B)-S_(C)).

FIG. 7 illustrates LLR Values as a function of the Signal Counts Metric (S_(B)-S_(C)) 700, for an exemplary Toshiba BiCS3 NAND flash memory device. In FIG. 7 , each point represents either a pair of either (LLR(B), S_(B)-S_(C)) (lower right portion of plot) or (LLR(C), S_(B)-S_(C)) (upper left portion) derived from a single codeword, using equation (1).

If such information (pairs) from enough codewords are collected, the correlation between LLR values and signal counts metric S_(B)-S_(C), as shown in FIG. 7 , can be represented by a linear fitted curve.

FIG. 8 illustrates a linear fitting 800 using linear curves 810-C and 810-B, to fit the (LLR(B), S_(B)-S_(C)) and (LLR(C), S_(B)-S_(C)) pairs of FIG. 7 , for the exemplary Toshiba BiCS3 NAND flash memory device.

The linear curves 810-B and 810-C are fitted for LLR(B) and LLR(C), respectively, and can be represented by equation (2) and (3),

$\begin{matrix} {{{{LLR}\left( {B,{S_{B} - S_{C}}} \right)} = {{a_{B}*\left( {S_{B} - S_{C}} \right)} + b_{B}}},} & (2) \\ {{{LLR}\left( {C,{S_{B} - S_{C}}} \right)} = {{a_{C}*\left( {S_{B} - S_{C}} \right)} + {b_{C}.}}} & (3) \end{matrix}$

The disclosed techniques for representing the correlation between LLR values and signal counts metric using linear curves 810-B and 810-C can be extended to employ non-linear curves as well, as described, for example, in U.S. patent application Ser. No. 16/144,65, filed Sep. 27, 2018, entitled “Page-Level Reference Voltage Parameterization For Solid State Storage Devices,” incorporated by reference herein in its entirety.

FIG. 9 is a flow chart illustrating an exemplary implementation of an error recovery process 900 for read parameter prediction, according to one embodiment of the disclosure. As shown in FIG. 9 , the exemplary 900 initially reads a codeword/page during step 910. A test is performed during step 920 to determine if the codeword/page is recovered by the decoder.

If it is determined during step 920 that the codeword/page is recovered by the decoder, then program control exits during step 920. If, however, it is determined during step 920 that the codeword/page is not recovered by the decoder, then three or more read values are obtained of the codeword/page during step 925.

During step 930, the exemplary error recovery process 900 processes the three or more read values of codeword/page to determine read parameters comprising (i) LLRs, and/or (ii) center V_(ref), as discussed further below.

FIG. 10 is a flow chart illustrating an exemplary implementation of an error recovery process 1000 using customized LLR values, according to one embodiment of the disclosure. Generally, after additional read operations are issued and soft decoding with default (predetermined) LLR LUT fails, the metric S_(B)-S_(C) is calculated and the customized LLR values are calculated using equations (2) and (3). The newly calculated LLR values are then used to map soft information (instead of using the predetermined LLR-LUTs shown in FIG. 5 ). Since the metric S_(B)-S_(C) is dynamically calculated/measured for each codeword (or page) and the LLR values are calculated in this manner as well. It can thus be shown that the exemplary error recovery process 1000 of FIG. 10 will yield a more accurate reliability level for the decoder. Note that, in some embodiments, the LLR estimation is accomplished with the existing multiple read operations without additional read operations.

As shown in FIG. 10 , the exemplary error recovery process 1000 initially issues a single read operation during step 1005. The hard information is then mapped to LLR values during step 1010 with a predetermined LLR-LUT for decoding (e.g., that maps bits to two values in some embodiments (e.g., −7 and 7)). Hard decoding is then performed during step 1015.

A test is performed during step 1020 to determine if the decoding succeeds. If it is determined during step 1020 that decoding succeeds, then program control exits during step 1070. If, however, it is determined during step 1020 that decoding does not succeed, then two additional read operations are issued during step 1025. A test is performed during step 1035 to determine if the decoding succeeds. If it is determined during step 1035 that decoding succeeds, then program control exits during step 1070. If, however, it is determined during step 1035 that that decoding does not succeed, then S_(B) and S_(C) are calculated during step 1040 using equation (1) and the metric S_(B)-S_(C) is calculated during step 1045. LLR(B) and LLR(C) values are computed during step 1050 using equations (2) and (3).

Soft Information is mapped to LLR Values with Computed LLRs during step 1055. A test is performed during step 1060 to determine if the decoding succeeds. If it is determined during step 1060 that decoding succeeds, then program control exits during step 1070. If, however, it is determined during step 1060 that decoding does not succeed, then other Error Recovery Actions are optionally performed during step 1065.

One or more aspects of the present disclosure recognize that the parameters a_(B), b_(B), a_(C) and b_(C) used by step 1050 of the error recovery process 1000 can be calculated using offline data and stored in memory (e.g. a DRAM).

FIG. 1 illustrates an exemplary LLR calculator 800 that uses the disclosed read parameter estimation techniques for a linear model to calculate LLR(B), according to at least one embodiment of the disclosure. As shown in FIG. 11 , to compute an LLR value for an exemplary page, the exemplary LLR calculator 1100 processes the metric S_(B)-S_(C) 1110, the page type 1120 (e.g., LSB/CSB/MSB/SLC); a region identifier 1130 (e.g., a die identifier); and/or one or more NAND conditions 840 (e.g., retention, P/E cycle, program/read temperature, etc.), to read the coefficients al and be from memory 1150 (e.g., a DRAM memory). Representative LLR(B) is computed by the exemplary LLR calculator 800 using equation (2). An implementation for computing LLR(C) would be similar to the implementation for LLR(B), as would be apparent to a person of ordinary skill in the art.

For a multi-level cell NAND (such as MLC, TLC or QLC), where for some page types multiple reference voltages (V_(ref) values) are involved, the parameters can be tuned for each individual V_(ref). FIG. 12 illustrates various regions for an exemplary LSB page of the exemplary Toshiba BiCS3 NAND flash memory device. For the LSB page of FIG. 12 , R₁ and R₅ are the two relevant V_(ref) values. The regions B₁, C₁, B₅ and C₅ are differentiable from the three-read patterns. Therefore, the linear fitting can be conducted independently to derive (a_(1B), b_(1B), a_(1C), b_(1C)) for R₁ and (a_(5B), b_(5B), a_(5C), b_(5C)) for R₅ such that,

$\begin{matrix} {{{{LLR}\left( {B_{i},{S_{iB} - S_{iC}}} \right)} = {{a_{iB}*\left( {S_{iB} - S_{iC}} \right)} + b_{iB}}},} & (4) \\ {{{{LLR}\left( {C_{i},{S_{iB} - S_{iC}}} \right)} = {{a_{iC}*\left( {S_{iB} - S_{iC}} \right)} + b_{iC}}},} & (5) \end{matrix}$ where S_(iB) and S_(iC) are the signal counts of region B_(i) and C_(i) and i ∈ {1,5}.

In some cases, the regions from different V_(ref) values are not differentiable. FIG. 13 illustrates various regions for a representative CSB page of the exemplary Toshiba BiCS3 NAND flash memory device, where R₂, R₄ and R₆ are the three relevant V_(ref) values. Without reading other pages, the three-read patterns can only measure B₄, C₄, B₂+B₆ and C₂+C₆. In other words, the corresponding regions of R₂ and R₆ are not differentiable.

In some embodiments, two methods can be applied when the corresponding regions for reference voltages R₂ and R₆ are not differentiable:

1) Apply a linear fitting for reference voltages R₂ and R₆ by using the same metric (S_(2B)+S_(6B))−(S_(2C)+S_(6C)). FIG. 14 illustrates an exemplary implementation 1400 for differentiating regions for reference voltages R₂ and R₆ for the representative CSB page of FIG. 13 without supporting pages (e.g., with the existing three read operations) by using the same LLR label for both regions of reference voltages R₂ and R₆ of FIG. 13 , according to an embodiment. Note that the regions B_(j) and C_(j) can be labelled by a three-read pattern. For example, with the convention of reading pattern [T_(l)T_(c)T_(r)], B₂ and B₆ share the same label of ‘011’; C₂ and C₆ share the same label of ‘001’; B₄ is labelled as ‘100’ and C₄ as ‘110’. Without supporting pages, the bin counts 1410 in these non-differentiable regions are established as follows: S₀₁₁=S_(2B)+S_(6B) and S₀₀₁=S_(2C)+S_(6C). Then, for reference voltages R₂ and R₆, the fitting becomes, at stages 1425-1 and 1425-2,

$\begin{matrix} {{{{LLR}\left( {B_{j},{S_{011} - S_{001}}} \right)} = {{a_{011}*\left( {S_{011} - S_{001}} \right)} + b_{011}}},} & (4) \\ {{{{LLR}\left( {C_{j},{S_{011} - S_{001}}} \right)} = {{a_{001}*\left( {S_{011} - S_{001}} \right)} + b_{011}}},} & (5) \end{matrix}$ where j ∈ {2,6}. Note that the same LLR values are applied to the ambiguous regions, e.g., LLR(B₂,S₀₁₁−S₀₀₁)=LLR(B₆,S₀₁₁−S₀₀₁)=LLR₀₁₁ and LLR(C₂,S₀₁₁−S₀₀₁)=LLR(C₆,S₀₁₁−S₀₀₁)=LLR₀₀₁. The coefficients as and bs are stored in registers 1420. The resulting LLR values are stored in an LUT 1430.

2) Read support pages to differentiate regions of R₂ and R₆. However, this method requires additional read operations. FIG. 15 illustrates an exemplary implementation 1500 for differentiating regions of reference voltages R₂ and R₆ for the representative CSB page of FIG. 13 with supporting pages (e.g., with additional read operations), according to some embodiments. In FIG. 15 , additional support pages are used help to differentiate regions coming from different thresholds. For example, S_(2,011) denotes the signal count 1510 of region B₂, while S_(6,011) denotes the signal count 1510 of region B₆. The corresponding LLR values (computed at stages 1525-1 and 1525-12 and are stored in the LUT 1530), such as LLR_(2,011) and LLR_(6,011), are also differentiable. In FIG. 15 , s represents different thresholds. With the supporting information, each threshold can calculate its LLR values individually. The coefficients as and bs are stored in registers 1520.

Note that, other type of fittings (e.g., a non-linear fitting) can also be applied for LLR estimation, in the manner described above. The metric is also not necessarily constrained to the difference of the signal counts between two regions specified above. Depending on the NAND characteristics, various fitting methods with various metrics can be applied.

The fitting parameters are calculated offline, but can also be updated on-the-fly whenever new samples are available, as would be apparent to a person of ordinary skill in the art.

Center V_(ref) Estimation

As noted above, the disclosed error recovery techniques can also process the three or more read values of a given codeword or page to determine a center V_(ref) read parameter, as discussed hereinafter. The signal counts of different regions provide insights into the relative location of the current center V_(ref) with respect to a substantially optimum value. Therefore, the signal count metric can also be used to estimate a more effective center V_(ref) read parameter, which is expected to reduce the errors in the raw data.

FIG. 16 illustrates the center V_(ref) read parameter as a function of the Signal Counts Metric (S_(B)-S_(C)) 1600, for the exemplary Toshiba BiCS3 NAND flash memory device. In FIG. 16 , each point represents a pair of (Vref, S_(B)-S_(C)) values. If such information (pairs) from enough codewords are collected, for example, the correlation between center V_(ref) values (with respect to a substantially optimal V_(ref)) and the signal counts metric S_(B)-S_(C), as shown in FIG. 16 , can be represented by a linear fitted curve 1620, which can be expressed by equation (6), as follows:

$\begin{matrix} {V = {\propto {{*\left( {S_{B} - S_{C}} \right)} + {\beta.}}}} & (6) \end{matrix}$ FIG. 17 is a flow chart illustrating an exemplary implementation of an error recovery process 1700 using customized center V_(ref) values, according to one embodiment of the disclosure. As shown in FIG. 17 , the exemplary error recovery process 1700 initially issues three read operations during step 1710. Thereafter, the signal counts, S_(B) and S_(C), are calculated during step 1720, and the signal counts metric, S_(B)-S_(C), is calculated during step 1730.

Equation (6) is employed during step 1740 to compute the center V_(ref) value, by obtaining the corresponding parameters ∝ and β from memory for the center V_(ref) calculation. During step 1750, T_(C) (current center Vref; see, e.g., FIG. 4 ) and V are used as the new center V_(ref) value for a single read operation or multiple read operations. Finally, additional error recovery (e.g., error correction decoding) is performed during step 1760.

It is noted that the linear fitting parameters can be tuned for each individual V_(ref), and various NAND conditions, as would be apparent to a person of ordinary skill in the art, in a manner Similar to the LLR estimation techniques described above.

Combination of LLR Estimation and Center V_(ref) Estimation

FIGS. 18A and 18B, collectively, are a flow chart illustrating an exemplary implementation of an error recovery process 1800 using customized LLR values and center V_(ref) values, according to one embodiment of the disclosure. As noted above, with three existing read operations, LLR values and center V_(ref), offset values can be calculated independently. The disclosed error recovery techniques can incorporate one or both of the customized LLR values and center V_(ref) values. When both values and center V_(ref) offset values are included, the execution order can be performed in either manner. In the exemplary embodiment of FIG. 18 , decoding is performed first using customized LLR values, followed by the new center V_(ref) offset values.

As shown in FIG. 18A, the exemplary error recovery process 1800 initially issues a single read operation during step 1805. The hard information is then mapped to LLR values during step 1810 (e.g., with a predetermined LLR-LUT (e.g., of FIG. 5 or FIG. 6 )). Hard decoding is then performed during step 1815.

A test is performed during step 1820 to determine if the decoding succeeds. If it is determined during step 1820 that decoding succeeds, then program control proceeds to FIG. 18B and exits during step 1898. If, however, it is determined during step 1820 that decoding does not succeed, then two additional read operations are issued during step 1825. A test is performed during step 1835 to determine if the decoding succeeds. If it is determined during step 1835 that decoding succeeds, then program control proceeds to FIG. 18B and exits during step 1898. If, however, it is determined during step 1835 that that decoding does not succeed, then S_(B) and S_(C) are calculated during step 1840 (e.g., using equation (1)). Program control then proceeds to FIG. 18B.

As shown in FIG. 18B, the exemplary error recovery process 1800 then calculates the metric S_(B)-S_(C) during step 1855. LLR(B) and LLR(C) values are computed during step 1860 (e.g., using equations (2) and (3)).

Soft Information is mapped to LLR Values with Computed LLRs during step 1865. A test is performed during step 1870 to determine if the decoding succeeds. If it is determined during step 1870 that decoding succeeds, then program control exits during step 1898. If, however, it is determined during step 1870 that decoding does not succeed, then Equation (6) is employed during step 1875 to compute the new center V_(ref) value (e.g., by obtaining the corresponding parameters ∝ and β from memory for the center V_(ref) calculation). During step 1880, T_(C) (current center Vref; see, e.g., FIG. 4 ) and V are used as the new center V_(ref) value for a single read operation or for multiple read operations.

During step 1885, hard and/or soft decoding is performed with predetermined or customized LLR values. A test is performed during step 1890 to determine if the decoding succeeds. If it is determined during step 1890 that decoding succeeds, then program control exits during step 1898. If, however, it is determined during step 1890 that decoding does not succeed, then additional error recovery (e.g., error correction decoding) is performed during step 1894.

FIG. 19 illustrates an exemplary parallel implementation of an error recovery process 1900 using customized LLR values and center V_(ref) values, according to an embodiment. Generally, the processing timeline for FIG. 19 proceeds from left to right, and downward. The exemplary error recovery process 1900 comprises a set of read operations 1910, a hardware acceleration block 1915 and a set of decode operations 1920. Thus, in the exemplary embodiment of FIG. 19 , the parallelism is achieved by using a dedicated hardware block 1915 to perform parameter estimation.

As shown in FIG. 19 , the exemplary parallel error recovery process 1900 initially performs a single read operation during step 1925 and then applies hard decoding during step 1930. Two additional read operations are performed during step 1935 and then a customized page LLR is computed by hardware acceleration block 1940, in accordance with the disclosed techniques. Conventional soft decoding is applied during step 1945 using default LLRs, while soft decoding is also applied in parallel during step 1950 using the customized LLRs computed by hardware acceleration block 1940, in accordance with the disclosed techniques.

As shown in FIG. 19 , additional support pages are read during step 1955 and hard decoding is applied during step 1960, using the techniques discussed above in conjunction with FIGS. 12 and 13. Customized wordline offsets are computed during step 1970 to compute the new center V_(ref) value.

The new center V_(ref) value is used for a single read operation during step 1975 and then hard decoding is applied during step 1980. Two additional read operations are performed during step 1985 and then a customized page LLR is computed by hardware acceleration block 1990, in accordance with the disclosed techniques. Conventional soft decoding is applied during step 1995 using default LLRs, while soft decoding is also applied in parallel during step 1998 using the customized LLRs computed by hardware acceleration block 1990, in accordance with the disclosed techniques.

Implementation Options

FIG. 20 illustrates an exemplary firmware implementation of an error recovery system 2000 using customized LLR values and center V_(ref) values, according to some embodiments. As shown in FIG. 20 , data is read from a flash memory 2010 and stored in a common read buffer 2015. A dedicated bin generation/accumulation block 2020 then measures the statistics for each bin (e.g., S_(B) and S_(C), for example). To accommodate a QLC format, for example, there are up to 64 bins 2030. In the embodiment of FIG. 20 with firmware intervention, the prediction of LLR LUTs and the new center V_(ref) offset are performed by firmware 2040.

The customized LLR values are stored in a digital LUT (DLUT) 2050 and used for LDPC decoding 2060 of the read values from buffer 2010. The new center V_(ref) offset 2070 is used for a new read operation applied to the flash memory 2010.

FIG. 21 illustrates an exemplary hardware implementation of an error recovery system 2100 using customized LLR values and center V_(ref) values, according to one or more embodiments. As shown in FIG. 21 , data is read from a flash memory 2110 and stored in a common read buffer 2120. A dedicated bin generation/accumulation block 2150 then measures the statistics for each bin (e.g., S_(B) and S_(C), for example). In the embodiment of FIG. 21 with a hardware implementation, the customized LLR values are stored in a DLUT 2160 and used for LDPC decoding 2170 of the read values from buffer 2120. The new center V_(ref) offset 2180 is used for a new read operation applied to the flash memory 2110.

In some embodiments, an important aspect of a hardware implementation is the generality and flexibility, as mapping between pages and symbols varies between flash vendors and flash generations. The disclosed architecture in FIG. 21 uses programmable tables to retain sufficient flexibility.

Assume that the hardware contains a mechanism to bin the result of three read operations with different threshold voltages. The binary values are then concatenated into three-bit words resulting in eight different values (0-7 decimal) which are used as address into bins. The bins are incremented every time a particular value is obtained resulting in a histogram of the different symbols. If supporting information is available, then separate groups of eight bins correspond to each combination of the supporting information.

Once sufficient statistics have been accumulated, the LLR values (and threshold voltage offsets) can be calculated by a state machine that relies on several tables loaded by firmware.

FIG. 22 illustrates exemplary hardware tables 2200 for supporting LLR calculations, according to one embodiment of the disclosure. As shown in FIG. 22 , the exemplary hardware tables 2200 comprise bins 2210, a first bin pointer 2220, pointers 2230, a second bin pointer 2240, types 2250 and coefficients 2260.

The exemplary hardware tables 2200 provide an implementation of the calculation discussed above in conjunction with FIG. 15 . Thus, the exemplary hardware tables 2200 differentiate regions of reference voltages R₂ and R₆ for the representative CSB page of FIG. 13 with supporting pages ‘1’ and ‘0’ (e.g., with additional read operations of pages ‘1’ and ‘0’). Bins 2210 correspond to the bin counts 1510, and the coefficients 2260 correspond to the registers 1520.

Generally, the bins table 2210, pointers table 2230 and types table 2250 are all addressed using the same bin pointer 2220. The pointers table 2230 is used to implement linked lists that enable sums and/or differences of arbitrary bin values. The types table 2250 allows the state machine to generate both constant LLR values (such as +/−7 for high confidence regions) and computed LLR values for the remaining regions. If the types table 2250 contains a constant field, then the entries are ‘c’, sign and magnitude of the constant. The pointer field 2230 contains a ‘p’, a sign bit indicating whether the accumulated bin value should be added or subtracted and a coefficient pointer (cp) providing an address for the coefficients table 2260.

For example, the LLR₁₁₀ value shown in FIG. 15 can be calculated by the following steps. Assume that the bin pointer 2220 has reached address 6. The type is then ‘p’ with a sign of +1, so a variable is initialized to +S₁₁₀. The bin pointer 2220 is then replaced with the value of the pointer table 2230 at address 6, which is 4. The type entry from table 2250 at address 4 is again ‘p’ with a sign of −1. The variable is then updated to +S₁₁₀-S₁₀₀. The bin pointer 2220 is again replaced by the value at address 4, which is 6. Since this is the original value, the process terminates with a calculation of the LLR value using the last entry of the types table 2250 at address 6 as a coefficient pointer to the coefficient table 2260. At address 6, this pointer is 3 which then enables the state machine to calculate the LLR₁₁₀ value as a₁₁₀*(+S₁₁₀-S₁₀₀)+b₁₁₀.

FIG. 23 is a flow chart illustrating an exemplary implementation of the state machine discussed in conjunction with FIG. 22 , according to one or more embodiments of the disclosure. As shown in FIG. 23 , the bin pointer (bp) 2220 is initialized to zero during step 2310. A test is performed during step 2315 to determine if the entry in the types table 2250 pointed to by the bin pointer 2220 is of type c or type p. If it is determined during step 2315 that the corresponding entry is type c, then a constant is written into the LUT during step 2320, and the bin pointer 2220 is incremented during step 2325. Program control returns to step 2315.

If, however, it is determined during step 2315 that the corresponding entry is type p, then a variable init_bp is initialized to the current value of the bin pointer 2220 during step 2330. A variable value is then set during step 2335 to the sign indicated in the entry in the types table 2250 pointed to by the bin pointer 2220, multiplied by the bin count value in the entry in the bin table 2210 pointed to by the bin pointer 2220. The bin pointer 2220 is then replaced during step 2340 with the value of the pointer table 2230 at the address pointed to by the bin pointer 2220.

A test is performed during step 2345 to determine if the bin pointer 2220 equals the variable init_bp. If it is determined during step 2345 that the bin pointer 2220 does not equal the variable init_bp, then program control returns to step 2335.

If, however, it is determined during step 2345 that the bin pointer 2220 does equal the variable init_bp, then the LLR value associated with the bin pointer 2220 is computed during step 2350, the new LLR value is written into the LUT during step 2355 and the bin pointer 2220 is incremented during step 2360. Program control then returns to step 2315.

It is noted that using a linked list results in a general solution where the number of terms in the expression is arbitrary (e.g., it is not limited to just two bin values).

Conclusion

In one or more embodiments of the disclosure, techniques are provided for read parameter prediction. It should be understood that the read parameter prediction techniques illustrated in FIGS. 1 through 23 are presented by way of illustrative example only, and should not be construed as limiting in any way. Numerous alternative configurations of system and device elements and associated processing operations can be used in other embodiments.

Illustrative embodiments disclosed herein can provide a number of significant advantages relative to conventional arrangements. For example, one or more embodiments provide a significantly improved codeword failure rate without increasing latency or complexity.

It is to be appreciated that the particular advantages described above and elsewhere herein are associated with particular illustrative embodiments and need not be present in other embodiments. Also, the particular types of read parameter prediction features and functionality as illustrated in the drawings and described above are exemplary only, and numerous other arrangements may be used in other embodiments.

As mentioned previously, at least portions of the disclosed read parameter prediction system may be implemented using one or more processing platforms. A given such processing platform comprises at least one processing device comprising a processor coupled to a memory. The processor and memory in some embodiments comprise respective processor and memory elements of a virtual machine or container provided using one or more underlying physical machines. The term “processing device” as used herein is intended to be broadly construed so as to encompass a wide variety of different arrangements of physical processors, memories and other device components as well as virtual instances of such components. For example, a “processing device” in some embodiments can comprise or be executed across one or more virtual processors. Processing devices can therefore be physical or virtual and can be executed across one or more physical or virtual processors. It should also be noted that a given virtual device can be mapped to a portion of a physical one.

The disclosed read parameter prediction arrangements may be implemented using one or more processing platforms. One or more of the processing modules or other components may therefore each run on a computer, storage device or other processing platform element. A given such element may be viewed as an example of what is more generally referred to herein as a “processing device.”

Referring now to FIG. 24 , one possible processing platform that may be used to implement at least a portion of one or more embodiments of the disclosure is shown. The processing platform 2400 in this embodiment comprises at least a portion of the given system and includes at least one processing device(s), denoted 2402-1, 2402-2, 2402-3, . . . 2402-D, which communicate with one another over a network 2404. The network 2404 may comprise any type of network, such as the Internet, a wireless area network (WAN), a local area network (LAN), a satellite network, a telephone or cable network, a cellular network, a wireless network such as WiFi or WiMAX, or various portions or combinations of these and other types of networks.

The processing device 2402-1 in the processing platform 2400 comprises a processor 2410 coupled to a memory 2412. The processor 2410 may comprise a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other type of processing circuitry, as well as portions or combinations of such circuitry elements. The memory 2412 may comprise random access memory (RAM), read only memory (ROM) or other types of memory, in any combination. The memory 2412 and other memories disclosed herein should be viewed as illustrative examples of what are more generally referred to as “processor-readable storage media” storing executable program code of one or more software programs.

Also included in the processing device 2402-1 is network interface circuitry 2414, which is used to interface the processing device with the network 2404 and other system components, and may comprise conventional transceivers.

The other processing devices 2402, if any, of the processing platform 2400 are assumed to be configured in a manner similar to that shown for processing device 2402-1 in the figure.

Again, the particular processing platform 2400 shown in the figure is presented by way of example only, and the given system may include additional or alternative processing platforms, as well as numerous distinct processing platforms in any combination, with each such platform comprising one or more computers, storage devices or other processing devices.

Multiple elements of the system may be collectively implemented on a common processing platform of the type shown in FIG. 24 , or each such element may be implemented on a separate processing platform.

Articles of manufacture comprising such processor-readable storage media are considered illustrative embodiments. A given such article of manufacture may comprise, for example, a storage array, a storage disk or an integrated circuit containing RAM, ROM or other electronic memory, or any of a wide variety of other types of computer program products. The term “article of manufacture” as used herein should be understood to exclude transitory, propagating signals. Numerous other types of computer program products comprising processor-readable storage media can be used.

Again, the particular processing platform 2400 shown in FIG. 24 is presented by way of example only, and the read parameter prediction system may include additional or alternative processing platforms, as well as numerous distinct processing platforms in any combination, with each such platform comprising one or more computers, servers, storage devices or other processing devices.

It should therefore be understood that in other embodiments different arrangements of additional or alternative elements may be used. At least a subset of these elements may be collectively implemented on a common processing platform, or each such element may be implemented on a separate processing platform.

Also, numerous other arrangements of computers, servers, storage devices or other components are possible in the read parameter prediction system. Such components can communicate with other elements of the read parameter prediction system over any type of network or other communication media.

As indicated previously, components of an information processing system as disclosed herein can be implemented at least in part in the form of one or more software programs stored in memory and executed by a processor of a processing device. For example, at least portions of the functionality of the processes of FIGS. 9, 10, 17, 18A, 18B and/or 23 are illustratively implemented in the form of software running on one or more processing devices.

It should again be emphasized that the above-described embodiments are presented for purposes of illustration only. Many variations and other alternative embodiments may be used. For example, the disclosed techniques are applicable to a wide variety of other types of information processing systems and read parameter prediction systems. Also, the particular configurations of system and device elements and associated processing operations illustratively shown in the drawings can be varied in other embodiments. Moreover, the various assumptions made above in the course of describing the illustrative embodiments should also be viewed as exemplary rather than as requirements or limitations of the disclosure. Numerous other alternative embodiments within the scope of the appended claims will be readily apparent to those skilled in the art. 

What is claimed is:
 1. A method, comprising: determining a correlation between optimal reference voltage offsets and a signal counts metric associated with a solid-state storage device; in response to a decoding failure of a codeword read from a first memory of the solid-state storage device, obtaining at least three read values of the codeword; calculating a signal counts metric value from the at least three reads; computing an optimal reference voltage offset from the signal counts metric and the correlation; determining a new center read reference voltage based on a current center reference voltage and the optimal reference voltage offset; and performing at least one subsequent read of the codeword following the decoding failure utilizing the new center read reference voltage.
 2. The method of claim 1, wherein at least two of the at least three read values are obtained from the first memory following the decoding failure.
 3. The method of claim 1, wherein the signal counts metric comprises a difference value between signal counts, each signal count indicating a number of bits falling in a particular region of a plurality of regions of the first memory defined by a plurality of read threshold voltages of memory cells of the first memory.
 4. The method of claim 3, wherein the plurality of regions comprises at least two regions adjacent to a first read threshold voltage and wherein one or more of the plurality of regions are differentiated using one or more additional read operations.
 5. The method of claim 1, wherein the correlation is characterized using a linear fitted curve of optimal reference voltage offsets to signal counts metric values.
 6. The method of claim 5, wherein a plurality of linear fitting parameters defining the correlation are stored in a second memory of the solid-state storage device, and wherein computing the optimal reference voltage offset from the signal counts metric and the correlation further comprises retrieving the plurality of linear fitting parameters from the second memory.
 7. The method of claim 1, wherein at least a portion of the step of processing the at least three read values is performed using one or more of a hardware acceleration block, firmware, a state machine and hardware.
 8. An apparatus, comprising: a first memory; and at least one processing device coupled to the first memory and operative to perform steps of: in response to a decoding failure of a codeword read from the first memory, obtaining at least three read values of the codeword, calculating a signal counts metric value from the at least three reads, computing an optimal reference voltage offset from the signal counts metric and a predetermined correlation between optimal reference voltage offsets and signal counts metric values associated with the first memory, determining a new center read reference voltage based on a current center reference voltage and the optimal reference voltage offset, and performing at least one subsequent read of the codeword following the decoding failure utilizing the new center read reference voltage.
 9. The apparatus of claim 8, wherein at least two of the at least three read values are obtained from the first memory following the decoding failure.
 10. The apparatus of claim 8, wherein the signal counts metric comprises a difference value between signal counts, each signal count indicating a number of bits falling in a particular region of a plurality of regions of the first memory defined by a plurality of read threshold voltages of memory cells of the first memory.
 11. The apparatus of claim 10, wherein the plurality of regions comprises at least two regions adjacent to a first read threshold voltage, and wherein one or more of the plurality of regions are differentiated using one or more additional read operations.
 12. The apparatus of claim 8, wherein the predetermined correlation is characterized using a linear fitted curve of optimal reference voltage offsets to signal counts metric values.
 13. The apparatus of claim 12, wherein a plurality of linear fitting parameters defining the predetermined correlation are stored in a second memory coupled to the at least one processing device, and wherein computing the optimal reference voltage offset from the signal counts metric and the predetermined correlation further comprises retrieving the plurality of linear fitting parameters from the second memory.
 14. The apparatus of claim 8, wherein at least a portion of the steps of calculating, computing, and determining is performed using one or more of a hardware acceleration block, firmware, a state machine and hardware.
 15. A storage controller comprising the apparatus of claim
 8. 16. A storage device comprising a controller coupled to a solid-state storage media, the controller configured to: in response to a decoding failure of a codeword read from the solid-state storage media, obtain at least three read values of the codeword; calculate a signal counts metric value from the at least three reads; compute an optimal reference voltage offset from the signal counts metric and a first correlation between optimal reference voltage offsets and signal counts metrics associated with the solid-state storage media, the first correlation based on a linear fitted curve of optimal reference voltage offsets to signal counts metric values; determine a new center read reference voltage based on a current center reference voltage and the optimal reference voltage offset; and perform at least one subsequent read of the codeword following the decoding failure utilizing the new center read reference voltage.
 17. The storage device of claim 16, wherein the controller is further configured to: calculate a plurality of dynamic log likelihood ratio (LLR) values based on the signal counts metric and a second correlation between LLR values and signal counts metric values associated with the solid-state storage media; and decode the codeword following the at least one subsequent read based at least in part upon the calculated plurality of dynamic LLR values.
 18. The storage device of claim 16, wherein a plurality of linear fitting parameters defining the first correlation are stored in a memory of the controller, and wherein computing the optimal reference voltage offset from the signal counts metric and the first correlation further comprises retrieving the plurality of linear fitting parameters from the memory.
 19. The method of claim 1, further comprising: calculating a plurality of dynamic log likelihood ratio (LLR) values based on the signal counts metric and a second correlation between LLR values and signal counts metric values associated with the first memory; and decoding the codeword following the at least one subsequent read based at least in part upon the calculated plurality of dynamic LLR values. 